AVR Instruction Set (by functional groups)

instr operands action description
BIT MANIPULATION - BY LOGIC FUNCTION
AND dreg, reg dreg = dreg (and) reg Logical AND
ANDI dreg, k8 dregh = dregh (and) k8 Logical AND with Immediate
OR dreg, reg dreg = dreg (or) reg Logical OR
ORI dreg, k8 dregh = dregh (or) k8 Logical OR with Immediate
EOR dreg, reg dreg = dreg (xor) reg Exclusive OR
COM dreg, dreg = not(dreg) One's Complement
BIT MANIPULATION - SET/CLEAR BITS
SBR dreg, k8 dregh = dregh (or) k8 Set Bit(s) in Register
CBR dreg, k8 dregh = dregh (or) not(k8) Clear Bit(s) in Register
SBI ioreg, bit ioreg[bit] = 1 Set Bit in I/O Register
CBI ioreg, bit ioreg[bit] = 0 Clear Bit in I/O Register
BIT MANIPULATION - SHIFT AND ROTATE
LSL dreg shift_left dreg, Logical Shift Left
LSR dreg shift_right dreg, Logical Shift Right
ROL dreg rotate_left dreg, Rotate Left Through Carry
ROR dreg rotate_right dreg, Rotate Right Through Carry
BIT MANIPULATION - ASSIGMENT
BST reg, bit temp_bit = reg[bit] Bit Store from Register to T
BLD dreg, bit dreg[bit] = temp_bit Bit load from T to Register
BIT MANIPULATION - OF STATUS REGISTER
BSET bit status[bit] = 1 Flag Set
BCLR bit status[bit] = 0 Flag Clear
SEC carry = 1 Set Carry
CLC carry = 0 Clear Carry
SEN negative = 1 Set Negative Flag
CLN negative = 0 Clear Negative Flag
SEZ zero = 1 Set Zero Flag
CLZ zero = 0 Clear Zero Flag
SEI interrupts_enabled = 1 Global Interrupt Enable
CLI interrupts_enabled = 0 Global Interrupt Disable
SES signed = 1 Set Signed Test Flag
CLS signed = 0 Clear Signed Test Flag
SEV overflow = 1 Set Two's Complement Overflow.
CLV overflow = 0 Clear Two's Complement Overflow
SET temp_bit = 1 Set T in reg
CLT temp_bit = 0 Clear T in reg
SEH half_carry = 1 Set Half Carry Flag in reg
CLH half_carry = 0 Clear Half Carry Flag in reg
ARITHMETIC
ADD dreg, reg dreg = dreg + reg Add without Carry
ADC dreg, reg dreg = dreg + reg + carry Add with Carry
SUB dreg, reg dreg = dreg - reg Subtract without Carry
SUBI dreg, k8 dregh = dregh - k8 Subtract Immediate
SBC dreg, reg dreg = dreg - reg - carry Subtract with Carry
SBCI dreg, k8 dregh = dregh - k8 - carry Subtract Immediate with Carry
NEG dreg dreg = 0 - dreg Two's Complement
INC dreg dreg = dreg + 1 Increment
DEC dreg dreg = dreg - 1 Decrement
ASR dreg shift_right_signed dreg Arithmetic Shift Right
SWAP dreg swap_nibbles dreg Swap Nibbles
TEST AND COMPARE
TST dreg dreg = dreg (and) dreg, Test for Zero or Minus
CPSE reg1, reg2 if reg1 == reg2 then skip Compare, Skip if Equal
CP reg1, reg2 reg1 - reg2 Compare register with register
CPI regh, k8 dregh - k8 Compare register with Immediate
CPC reg1, reg2 reg1 - reg2 - carry Compare with Carry
CONDITIONAL JUMP AND SKIP
SBRC reg, bit if reg[bit] = 0 then skip Skip if Bit in Register Cleared
SBRS reg, bit if reg[bit] = 1 then skip Skip if Bit in Register is Set
SBIC ioreg, bit if ioreg[bit] = 0 then skip Skip if Bit in I/O Register Cleared
SBIS ioreg, bit if ioreg[bit] = 1 then skip Skip if Bit in I/O Register is Set
BRBS bit, offset if status[bit] = 1 then jump offset Branch if Status Flag Set
BRBC bit, offset if status[bit] = 0 then jump offset Branch if Status Flag Cleared
BREQ offset if equal then jump offset Branch if Equal
BRNE offset if not equal then jump offset Branch if Not Equal
BRCS offset if carry then jump offset Branch if Carry Set
BRCC offset if not carry then jump offset Branch if Carry Cleared
BRSH offset if >= then jump offset Branch if Same or Higher
BRLO offset if < then jump offset Branch if Lower
BRMI offset if negative then jump offset Branch if Minus
BRPL offset if not negative then jump offset Branch if Plus
BRGE offset if signed >= then jump offset Branch if Greater or Equal, Signed
BRLT offset if signed < then jump offset Branch if Less Than Zero, Signed
BRHS offset if half_carry then jump offset Branch if Half Carry Flag Set
BRHC offset if not half_carry then jump offset Branch if Half Carry Flag Cleared
BRTS offset if temp_bit = 1 then jump offset Branch if T Flag Set
BRTC offset if temp_bit = 0 then jump offset Branch if T Flag Cleared
BRVS offset if overflow then jump offset Branch if Overflow Flag is Set
BRVC offset if not overflow then jump offset Branch if Overflow Flag is Cleared
BRIE offset if interrupts_enabled = 1 then jump offset Branch if Interrupt Enabled
BRID offset if interrupts_enabled = 0 then jump offset Branch if Interrupt Disabled
INCONDITIONAL jump
RJMP offset pc = pc + offset + 1 Relative jump
IJMP pc = z Indirect jump to (Z)
SUBROUTINES
RCALL offset push(pc+1); pc = pc + offset + 1 Relative Subroutine Call
ICALL push(pc+1); pc = z Indirect Call to (Z)
RET pop(pc) Subroutine Return
RETI pop(pc); status[intr_enabled] = 1 Interrupt Return
PUSH reg push(reg) Push Register on Stack
POP dreg pop(dreg) Pop Register from Stack
ASSIGMENT
CLR dreg dreg = 0 Clear Register
SER dreg dreg = 255 Set Register
LDI dreg, k8 dreg = k8 Load Immediate
MOV dreg, reg Copy Register
IN dreg, ioreg dreg = ioreg In from I/O Location
OUT ioreg, reg ioreg = reg Out to I/O Location
ASSIGMENT - USING POINTERS
LD dreg, x dreg = [x] Load Indirect
LD dreg, x+ dreg = [x]; x = x + 1 Load Indirect and Post-Increment
LD dreg, -x x = x - 1; dreg = [x] Load Indirect and Pre-Decrement
LD dreg, y dreg = [y] Load Indirect
LD dreg, y+ dreg = [y]; y = y + 1 Load Indirect and Post-Increment
LD dreg, -y y = y - 1; dreg = [y] Load Indirect and Pre-Decrement
LD dreg, z dreg = [z] Load Indirect
LD dreg, z+ dreg = [z] ; z = z + 1 Load Indirect and Post-Increment
LD dreg, -z z = z - 1 ; dreg = [z] Load Indirect and Pre-Decrement
LDS dreg, k dreg = [k] Store Direct from SRAM
ST x, reg [x] = reg Store Indirect
ST x+, reg [x] = reg ; x = x + 1 Store Indirect and Post-Increment
ST -x, reg x = x - 1 ; [x] = reg Store Indirect and Pre-Decrement
ST y, reg [y] = reg Store Indirect
ST y+, reg [y] = reg ; y = y + 1 Store Indirect and Post-Increment
ST -y, reg y = y - 1 ; [y] = reg Store Indirect and Pre-Decrement
ST z, reg [z] = reg Store Indirect
ST z+, reg [z] = reg ; z = z + 1 Store Indirect and Post-Increment.
ST -z, reg z = z - 1 ; [z] = reg Store Indirect and Pre-Decrement
STS k, reg [k] = reg Store Direct to SRAM
SPECIAL
BREAK break Break
NOP nop No Operation
SLEEP sleep Sleep
WDR watchdog_reset Watchdog Reset

Legend

symbol description range
k8 8-bit value [0..255]
bit 3-bit bit number [0..7]
offset-7 7-bit value [-64..+63]
offset-12 12-bit value [-2048..+2047]
reg, reg1, reg2 register [0..31]
regh high register [16..31]
dreg destination register [0..31]
dregh destination high register [16..31]
ioreg I/O register [0..63]